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CD4042BMS
December 1992
CMOS Quad Clocked "D" Latch
Pinout
CD4042BMS TOP VIEW
Features
* High-Voltage Type (20V Rating) * Clock Polarity Control * Q and Q Outputs * Common Clock * Low Power TTL Compatible * Standardized Symmetrical Output Characteristics * 100% Tested for Quiescent Current at 20V * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC * 5V, 10V and 15V Parametric Ratings * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Q4 1 Q1 2 Q1 3 D1 4 CLOCK 5 POLARITY 6 D2 7 VSS 8 NC = NO CONNECTION
16 VDD 15 Q4 14 D4 13 D3 12 Q3 11 Q3 10 Q2 9 Q2
Functional Diagram
D1 4 2 3 D2 7 10 9 D3 13 11 12 D4 14 1 15 CLOCK 5 CL Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4
Applications
* Buffer Storage * Holding Register * General Digital Logic
Description
CD4042BMS types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p- channel output devices is balanced and all outputs are electrically identical. Information present at the data input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the outputs until an opposite CLOCK transition occurs. The CD4042BMS is supplied in these 16 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1E H6W
POLARITY 6 VDD VSS 16 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3310
7-868
Specifications CD4042BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP Package . . . . . . . . . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 2 200 2 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC 3.5 11 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
1.5 4 -
V V V V
NOTES: 1. All voltages referenced to device GND. 2. Go/no go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-869
Specifications CD4042BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN o
PARAMETER Propagation Delay (Note 2) Data in to Q Propagation Delay (Note 2) Data in to Q Propagation Delay (Note 2) Clock to Q Propagation Delay (Note 2) Clock to Q Transition Time (Note 2) NOTES:
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPHL4 TPLH4 TTHL TTLH
CONDITIONS (NOTES 1, 2) VDD = 5V, VIN = VDD or GND
MAX 220 297 300 405 450 608 500 675 200 270
UNITS ns ns ns ns ns ns ns ns ns ns
+25oC +125 C, -55 C +25oC +125oC, -55oC
o
-
+25oC +125oC, -55oC +25oC +125 C, -55 C
o o
-
1. VDD = 5V, CL = 50pF, RL = 200K, input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High VOL VOL VOH VOH IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VIH VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25 C, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7
MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 -
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V
7-870
Specifications CD4042BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Data in to Q Propagation Delay Data in to Q Propagation Delay Clock to Q Propagation Delay Clock to Q Transition Time Clock Input Rise and Fall Time (Note 4) Minimum Data Setup Time Minimum Data Hold Time SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPHL3 TPLH3 TPLH4 TPHL4 TTHL TRCL TFCL TS CONDITIONS VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K. 4. * Not sensitive TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V TW VDD = 5V VDD = 10V VDD = 15V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC MIN MAX 110 80 150 100 200 160 230 180 100 80 * * * 50 30 25 120 60 50 200 100 60 7.5 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
7-871
Specifications CD4042BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.2A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. 1.5% parametric, 3% functional; cumulative for static 1 and 2. METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 METHOD 5005 PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 1 - 3, 9 - 12, 15 1 - 3, 9 - 12, 15 1 - 3, 9 - 12, 15 GROUND 4 - 8, 13, 14 8 8 8 VDD 16 4 - 7, 13, 14, 16 6, 16 4 - 7, 13, 14, 16 1 - 3, 9 - 12, 15 5 4, 7, 13, 14 9V -0.5V 50kHz 25kHz
7-872
Specifications CD4042BMS Logic Diagram
ONE OF FOUR LATCHES CL
*
D1 4 TG CL CL 2 Q1
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION NETWORK VDD CONTROL
TG
3
Q1
CL P
*
CLOCK 5 P VSS TG CL TG CL
P
*
POLARITY 6 P P
LOGIC BLOCK DIAGRAM
TRUTH TABLE CLOCK 0 POLARITY 0 0 1 1 1 Q D LATCH D LATCH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
873
CD4042BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5
0
0 -5 -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC 175 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 75 50 15V 25 10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC 175 150 SUPPLY VOLTAGE (VDD) = 5V 125 100 10V 75 50 15V 25
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 5. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - DATA TO Q
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - DATA TO Q
7-874
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
0
CD4042BMS Typical Performance Characteristics
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 300
(Continued)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
300
250 SUPPLY VOLTAGE (VDD) = 5V 200 150 10V 100 50 AMBIENT TEMPERATURE (TA) = +25oC 0 20 40 60 80 100 120 140 15V
250
SUPPLY VOLTAGE (VDD) = 5V
200 150
10V 15V
100 50
AMBIENT TEMPERATURE (TA) = +25oC 0 20 40 60 80 100 120 140
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - CLOCK TO Q
POWER DISSIPATION PER DEVICE (PD) (W) 106 105 104 103 10V 10V 102 10 1 103 104 105 106 107 5V CL = 50pF CL = 15pF SUPPLY VOLTAGE (VDD) = 15V
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE - CLOCK TO Q
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
0 0
20
INPUT FREQUENCY (fI) (kHz)
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY
FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE
NOTE 1 CLOCK CL NOTE 2 LATCH LOW DATA LATCH HIGH DATA tPHL, tPLH D TO Q OR Q tPHL, tPLH CL TO Q OR Q
Chip Dimensions and Pad Layout
DATA INPUT D
tS
tH
Q OUTPUT
LOW DATA LATCHED HIGH DATA LATCHED
NOTES: 1. For positive clock edge, input data is latched when polarity is low. 2. For negative clock edge, input data is latched when polarity is high.
FIGURE 11. DYNAMIC TEST PARAMETERS
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated Grid graduations are in mils (10-3 inch).
7-875

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